In modern computer and software applications there is increasingly a demand for ever larger volumes of data to be processed in an ever shorter time. Large scale integrated memories, such as DRAM memories for example, are used for storing the data. In order, then, to meet the aforementioned demand for an ever higher speed when processing data, it is necessary, in the case of such a semiconductor memory, for said data to be written to the memory and read out from said memory again appropriately rapidly.
As development advances in the field of integrated circuits, the operating frequency thereof rises, too, so that the data can be processed appropriately rapidly.
What is more, semiconductor memories also exist which are specially designed for high data rates. One representative of such a semiconductor memory is the so-called DDR-DRAM memory, where DDR stands for “double data rate”. Whereas in conventional semiconductor memories write and read operations are performed only upon the rising edge or the falling edge of a clock signal, in DDR semiconductor memories data are read out from the semiconductor memory and written to the semiconductor memory again both upon the rising edge and upon the falling edge of the clock signal. A double data rate is thus realized.
In the case of these DDR-DRAM semiconductor memories, the double data rate present externally at the semiconductor memory is converted internally into a single data rate and written in parallel to the semiconductor memory. In the case of a read access, however, the data present in parallel internally in the semiconductor memory have to be converted into a serial data stream again. For this purpose, the semiconductor memory or the interface circuit thereof is equipped with a parallel-to-serial converter—referred to hereinafter just as parallel-serial converter for short. An integrated circuit with an interface circuit having such a parallel-serial converter is described in U.S. Pat. No. 6,317,372.
In the simplest case, a parallel-serial converter is designed as a controllable shift register. A parallel-serial converter has a number of cascade-connected flip-flops corresponding to the number of input terminals. Furthermore, a control signal generated by means of a multiplexer may be provided for controlling the shift register. The construction and the method of operation of such a parallel-serial converter designed as a controllable shift register are known in many instances and described for example in Kories, Schmidt-Walter, Taschenbuch der Elekrotechnik, [Pocketbook of electrical engineering], Wissenschaftlicher Verlag Harri Deutsch GmbH, 5th corrected edition, 2003.
FIG. 1 uses a simple block diagram to show a simplified illustration of a generally known parallel-serial converter. The parallel-serial converter has four input terminals 1–4 and a single output terminal 5. Furthermore, four controllable inverters 7–10 arranged in parallel with one another are provided, which can respectively be controlled by means of control signals RI0, FA0, RI1, FA1. Data D0–D3 are present in parallel at the respective input terminals 1–4 and are read into a respective inverter 7–10 successively by means of control signals RI0, FA0, RI1, FA1 and applied to the common storage node 11. Two further inverters 12, 13 are connected downstream of the storage node 11. Furthermore, a feedback inverter 14 is provided, which is connected back-to-back with respect to the inverter 12 and is intended to hold the last state of the inverter 12 and thus the last state at the storage node 11.
FIG. 2 shows a signal timing diagram illustrating the sequence of the clock signal CLK, the control signals RI0, FA0, RA1, FI1 and the serial data signal Dout at the output 5 of the known circuit arrangement from FIG. 1. By means of latching the data D0–D3, the parallel-serial converter serializes the data signals D0–D3 present in parallel on the input side. The last state, that is to say the state assigned to the data packet D3, is held after the process of reading out the data signals D0–D3 has ended, that is to say at the instant t3. The storage node 11 then has said last state even when a read access does not actually take place and, consequently, no data actually have to be converted in the parallel-serial converter. The state is then held until a renewed memory access takes place, that is to say at the instant t4 in the present example.
Distortions of the data read out may occur during the conversion of the data, as well as during the driving of the data via the read line. The parallel-serial converter is arranged in the read part of the data path as the last circuit part directly upstream of the output driver. A distortion caused in whatever manner would have a serious effect on the data transmission since said distortion is equally concomitantly transmitted via the output driver. The arrangement of the parallel-serial converter directly upstream of the output driver thus makes it indispensable for the signal shape provided on the output side to be distorted as little as possible by the parallel-serial converter since otherwise a high quality of the data transmitted via the read part of the data path to the microcontroller is no longer ensured.
Large distortions in the data to be transmitted and thus a reduced quality furthermore has the effect of greatly restricting the maximum operating frequency as a result since the temporal width of an individual data eye 6 to be transmitted is blurred to a greater or lesser extent in the case of such distortions. A defined transition from one data eye 6 to the next is then no longer discernible as such, or is discernible as such only with very great difficulty, by the microcontroller that processes the data read out, with the result that, overall, a read-out of serial data present in dedicated fashion is no longer ensured.
The abovementioned distortions are undesirable but can never be entirely avoided. Said distortions should nonetheless be kept as low as possible. In the case of known parallel-serial converters in accordance with FIG. 1, the feedback inverter 14 makes the principal contribution to the corruption of the serially transmitted data signals and thus to the aforementioned distortions. In order to be able to hold the last state, said feedback inverter 14 must be “exaggerated” as it were, that is to say it must be made smaller than the inverter 12. However, this inevitably leads to the distortions.
The abovementioned distortions are dependent in particular on process fluctuations, that is to say that the greater the process fluctuations in the production of the feedback inverter 14, the more distortions in the transmitted data signals are to be reckoned with. However, said process fluctuations will have a more and more serious effect primarily in the case of future memory technologies in which the trend is toward ever smaller feature sizes, so that ever greater distortions in the data to be transmitted are to be reckoned with in this case.
This is a state which, understandably, is to be avoided.